1. Field of the Invention
The present invention relates to a semiconductor device and a method of controlling the semiconductor device, and more particularly, to a semiconductor device having a test mode and a method of controlling the semiconductor device having the test mode.
2. Description of Related Art
A plurality of semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) are often used in the state of being mounted on a module substrate. Therefore, in the stages of the development of semiconductor memories, there is the need to perform an operation test on semiconductor memory devices in the state of being mounted on a module substrate, and perform timing adjustment and the like in accordance with the test results. However, in the stages of semiconductor memory development, the number of semiconductor chips that can be subjected to the evaluation tests do not exist in large, and therefore, it is difficult to mount only semiconductor memory devices under development on a module substrate. In view of this, there has been a conventionally utilized method by which only one semiconductor memory device under development is mounted on a module substrate on which semiconductor memory devices already mass-produced are mounted, and this one semiconductor memory device is accessed.
On the module substrate, however, address terminals and command terminals are commonly connected among the respective semiconductor memory devices. Therefore, it is not possible to enter only a specific chip into a test mode. As a result, when the target chip enters the test mode, all the other chips also enter the test mode, and the chips cannot be adjusted independently of one another. Also, in a case where different test codes are used between mass-produced chips and chips under development, a chip that is not a target chip may enter an unintended test mode.
Japanese Patent Application Laid-Open No. 2007-323723 discloses a method of accessing semiconductor memory devices on a module substrate independently of one another.
A semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2007-323723 is capable of accessing respective chips independently of one another by using defective addresses replaced with redundant cells as the IDs of the respective chips. The excellent feature of this method is that not only a specific chip on a module substrate can be accessed independently of the other chips, but also the other chips can be accessed independently of one another. By the method disclosed in Japanese Patent Application Laid-Open No. 2007-323723, on the other hand, after a defective address is read by using a roll-call circuit, the read defective address needs to be analyzed. Therefore, the procedures are somewhat complicated. In view of this, the method is not necessarily an optimum method to be used in a case where only one semiconductor memory device under development is mounted on a module substrate on which mass-produced semiconductor memory devices are mounted, and only the semiconductor memory device under development is put into the test mode, as described above.